1 ? fn7172.2 caution: these devices ar e sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a tradem ark owned by intersil corporation or one of its subsidiaries. copyright ? intersil americas inc. 2003, 2008, 2010. all rights re served. elantec is a registered trademark of elantec semicond uctor, inc. all other trademarks mentioned are the property of their respective owners. manufactured under u.s. patent 5,528,303. el4581 sync separator, 50% slice, s-h, filter the el4581 extracts timing information from standard negative going video sync found in ntsc, pal and secam broadcast systems. it can also be used in non standard formats and with computer graphics systems at higher scan rates, by adjusting a single external resistor. when the input does not have correct serration pulses in the vertical interval, a default ve rtical output is produced. outputs are composite sync, ve rtical sync, burst/back porch output, and odd/even output. the later operates only in interlaced scan formats. the el4581 provides a reliable method of determining correct sync slide level by sett ing it to the mid-point between sync tip and blanking level at the back porch. this 50% level is determined by two internal self timing sample and hold circuits that track sync tip and back porch levels. this also provides a degree of hum and noise rejection to the input signal, and compensates for varying input levels of 0.5v p-p to 2.0v p-p . a built in linear phase, third orde r, low pass filter attenuates the chroma signal in color syst ems to prevent incorrectly set color burst from disturbing the 50% sync slide. this device may be used to replace the industry standard lm1881, offering improved performance and reduced power consumption. the el4581 video sync separator is manufactured using elantec?s high performance analog cmos process. pinout el4581 (8 ld soic, pdip) top view features ? ntsc, pal and secam sync separation ? single supply, +5v ? precision 50% slicing, internal caps ? built-in color burst filter ? decodes non-standard verticals ? pin compatible with lm1881 ? low power ? typically 1.5ma supply current ? resistor programmable scan rate ? few external components ? available in 8 ld pdip and soic packages ? pb-free available (rohs compliant) applications ? video special effects ? video test equipment ? video distribution ? displays ?imaging ? video data capture ? video triggers demo board a dedicated demo board is not available. however, this device can be placed on the el4584/5 demo board. 1 2 3 4 8 7 6 5 composite sync out composite video in vertical sync out gnd vdd 5v odd/even output rset burst/back porch output ordering information part number part marking temp. range package pkg. dwg. # el4581cn el4581cn -40c to +85c 8 ld pdip mdp0031 el4581cs* 4581cs -40c to +85c 8 ld soic mdp0027 el4581csz* (note) 4581csz -40c to +85c 8 ld soic (pb-free) mdp0027 *add ?-t7? or ?-t13? suffix for tape and reel. please refer to tb347 for details on reel specifications. note: these intersil pb-free plastic packaged products employ special pb-free material sets; molding compounds/die attach materials and 100% matte tin plate plus anneal - e3 termination finish, which is rohs compliant and compatible with both snpb and pb-free soldering operations. intersil pb-free products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. data sheet november 12, 2010
2 fn7172.2 november 12, 2010 absolute maxi mum ratings (t a = +25c) thermal information v cc supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7v storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c pin voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to v cc +0.5v operating conditions operating temperature range . . . . . . . . . . . . . . . . .-40c to +85c maximum power dissipation. . . . . . . . . . . . . . . . . . . . . . . . . see curves maximum junction temperature. . . . . . . . . . . . . . . . . . . . . . . . . +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp caution: do not operate at or near the maximum ratings listed fo r extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. important note: all parameters having min/max specifications are guaranteed. typical values are for information purposes only. u nless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: t j = t c = t a dc electrical specifications unless otherwise stated, v dd = 5v, t a = +25c, r set = 680k . parameter description temp (c) min (note 7) typ max (note 7) unit i dd v dd = 5v (note 1) +25 0.75 1.7 3 ma clamp voltage pin 2, unloaded +25 1.3 1.5 1.9 v discharge current pin 2 = 2v +25 6 10 20 a clamp charge current pin 2, v in = 1v +25 2 3 ma ref voltage pin 6, v dd = 5v (note 2) +25 1.5 1.8 2.1 v v ol output low voltage i ol = 1.6ma +25 800 mv v oh output high voltage i oh = -40a +25 4 v i oh = -1.6ma +25 2.4 v notes: 1. no video signal, outputs unloaded. 2. tested for v dd 5v 5%. dynamic specifications v dd = 5v, iv p-p video, t a = +25c, c l = 15pf, i oh = -1.6ma, i ol = 1.6ma. signal voltages are peak to peak. parameter description temp (c) min (note 7) typ max (note 7) unit vertical sync width, t vs (note 3) +25 190 230 300 s burst/back porch width, t b (note 3) +25 2.5 3.5 4.5 s vertical sync default delay t vsd +25405570s filter attenuation f in = 3.4mhz (note 4) +25 24 db composite sync prop delay v in - composite sync (note 3) +25 260 400 ns input dynamic range peak-to-peak ntsc signal (note 5) +25 0.5 2 v slice level input voltage = 1v p-p +25405060 % (note 6) full 40 50 60 % notes: 3. c/s, vertical and burst outputs are all active low (v oh = 2.4v, v ol = 0.8v). 4. attenuation is a function of r set (pin 6). 5. typical min is 0.3v p-p . 6. refers to threshold level of sync tip to back porch amplitude. 7. parts are 100% tested at +25c. over-temperature limits established by characterizati on and are not production tested. el4581
3 fn7172.2 november 12, 2010 pin descriptions pin number pin name function 1 composite sync out composite sync pulse output. sync pulses start on a falling edge and end on a rising edge. 2 composite video in ac coupled composite video input. sync tip mu st be at the lowest potential (positive picture phase). 3 vertical sync out vertical sync pulse output. the falling ed ge of vert sync is the start of the vertical period. 4 gnd supply ground. 5 burst/back porch output burst/back porch outpu t. low during burst portion of composite video. 6 rset (note 8) an external resistor to ground sets all inte rnal timing. 681k, 1% resistor will provide correct timing for ntsc signals. 7 odd/even output odd/even field output. low during odd fields, high during even fiel ds. transitions occur at start of vert sync pulse. 8 vdd 5v positive supply. (5v) note: 8. r set must be a 1% resistor. typical performance curves figure 1. r set vs horizontal frequency figure 2. back porch clamp, on-time vs r set figure 3. vertical pulse width vs r set figure 4. vertical default delay, time vs r set figure 5. vertical pulse width vs temperature figure 6. supply current vs temperature 1000 900 800 700 600 500 400 300 200 100 10 15 20 25 30 35 40 45 50 frequency (khz) r set (k ) clamp time (s) 02 46810 200 400 600 800 1000 0 r set (k ) 200 400 600 800 1000 0 0 200 400 100 300 500 vertical pulse width (s) r set (k ) 200 400 600 800 1000 0 r set (k ) delay time (s) 04080 20 60 100 150 200 250 300 350 pulse width (s) -55 5 65 -25 35 95 125 temperature (c) 0.5 1.0 1.5 2.0 -55 5 65 -25 35 95 125 temperature (c) supply current (ma) el4581
4 fn7172.2 november 12, 2010 figure 7. package power dissipation vs ambient temperature figure 8. package power dissipation vs ambient temperature figure 9. input signal = 300mv p-p , el4581 filter characterisitic constant delay 240ns typical performance curves 2.0 1.8 1.6 1.4 1.2 0.8 0.6 0.4 0.2 0 power dissipation (w) 1.0 0 25 50 75 100 125 150 package power dissipation vs ambient temperature jedec jesd51-7 high effective thermal conductivity test board ambient temperature (c) 85 1.471w 1.136w so8 ja = 110c/w pdip8 ja = 85c/w 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 025 50 75 100 125 150 package power dissipation vs ambient temperature jedec jesd51-3 low effective thermal conductivity test board ambient temperature (c) power dissipation (w) 1.25w 781mw 85 so8 ja = 160c/w pdip8 ja = 100c/w -25 -20 -15 -5 0 -30 -35 -10 100k 2m 10m 1m 4m frequency (hz) output (db) el4581
5 fn7172.2 november 12, 2010 timing diagrams notes: 9. the composite sync output reproduces all the video input sync pulses, with a propagation delay. 10. vertical sync leading edge is coincident with the first vertical serration pulse leading edge, with a propagation delay. 11. odd-even output is low for even field, and high for odd field. 12. back porch goes low for a fixed pulse wi dth on the trailing edge of video input sync pulses. note that for serration pulses during vertical, the back porch starts on the rising edge of the serration pulse (with propagation delay). figure 10. start of field one pre-equalizing pulse interval h sync interval pulse interval post-equalizing ref subcarrier phase, color field one time 1.5s230s t1 field one +h -0 1271s +63.5s -0s ) ( (*see note) see fig 4 see fig 2, 3 vertical blanking interval = 20h 3h 3h 3h 1 2 3 4 5 6 7 8 9 10 19 20 21 h h vertical sync pulse interval 9 line vertical interval h 0.5h h signal 1b. composite sync output, pin 1 signal 1c. vertical sync output, pin 3 signal 1d. odd-even output, pin 7 signal 1e. back porch output, pin 5 signal 1a. composite vi deo input, field one el4581
6 fn7172.2 november 12, 2010 timing diagrams (continued) slice level 50% comp sync prop delay t cs signal 2a. composite video input signal 2b. composite sync output signal 2c. vertical sync output signal 2d. odd-even output signal 2e. burst/back porch output t cs-vs comp sync vert sync delay comp sync delay odd/even t cs-oe t bd burst delay burst width t b figure 10. figure 11. signal 3a. composite video input signal 3b. vertical sync output t vsd lines vert sync default delay (no vertical sync pulses) 2 3 4 5 el4581
7 fn7172.2 november 12, 2010 description of operation a simplified block diagram is shown in figure 13. the following description is intended to provide the user with sufficient information to be ab le to understand the effects that the external components and signal conditions have on the outputs of the integrated circuit. the video signal is ac coupled to pin 2 via the capacitor c 1 , nominally 0.1f. the clamp circuit a1 will prevent the input signal on pin 2 going any more negative than 1.5v, the value of reference voltage v r1 . thus the sync tip, the most negative part of the video waveform, will be clamped at 1.5v. the current source i 1 , nominally 10a, charges the coupling capacitor during the remaining portion of the h line, approximately 58s for a 15.75khz timebase. from i?t = c?v, the video time-constant can be calculated. it is important to note that the charge taken from the capacitor during video must be replaced during the sync tip time, which is much shorter, (ratio of x12.5). the co rresponding current to restore the charge during sync will therefore be an order of magnitude higher, and any resistance in series with c 1 will cause sync tip crushing. for this reason, the internal series resistance has been minimized and external high resistance values in series with the input coupling capacitor should be avoided. the user can exercise some control over the value of the input time constant by introducing an external pull-up resistance from pin 2 to the 5v supply. the maximum voltage across the resistance will be v dd less 1.5v, for black level. for a net discharge current greater than zero, the resistance should be greater than 450k. this will have the effect of increasing the ti me constant and reducing the degree of picture tilt. the current source i 1 directly tracks reference current i tr and thus increases with scan rate adjustment, as explained later. the signal is processed through an active 3-pole filter (f1) designed for minimum ripple with constant phase delay. the filter attenuates the color burst by 24db and eliminates fast transient spikes without sync crushing. an external filter is not necessary. the filter also amplifies the video signal by 6db to improve the detection ac curacy. note that the filter cut-off frequency is a function of r set through i ot and is proportional to i ot . internal reference voltages (block v ref ) with high immunity to supply voltage variation are derived on the chip. reference v r4 with op amp a2 forces pin 6 to a reference voltage of 1.7v nominal. consequently, it can be seen that the external resistance r set will determine the value of the reference current i tr . the internal resistance r 3 is only about 6k , much less than r set . all the internal timing functions on the chip are referenced to i tr and have excellent supply voltage rejection. comparator c2 on the input to the sample and hold block (s/h) compares the leading and trailing edges of the sync pulse with a threshold voltage v r2 , which is referenced at a figure 12. standard (ntsc input) h. sync detail composite sync output, pin 1 depends on width of input sync at 50% points v clamp input dynamic range 0.5v to 2v back porch output, pin 5 v slice sync level 50% t cs video 100 ire 40 ire sync t bd white level black level blanking level t b sync tip color burst 40 ire el4581
8 fn7172.2 november 12, 2010 fixed level above the clamp voltage v r1 . the output of c2 initiates the timing one-shots for gating the sample and hold circuits. the sample of the sync tip is delayed by 0.8s to enable the actual sample of 2s to be taken on the optimum section of the sync. pulse tip. the acquisition time of the circuit is about three horizontal lines. the double poly cmos technology enables long time constants to be achieved with small high quality on-chip capacitors. the back porch voltage is similarly derived from the trailing edge of sync, which also serves to cut off the tip sample if the gate time exceeds the tip period. note t hat the sample and hold gating times will track rset through i ot . the 50% level of the sync tip is derived, through the resistor divider r 1 and r 2 , from the sample and held voltages v tip and v bp , and applied to the plus input of comparator c1. this comparator has built in hysteresis to avoid false triggering. the output of c2 is a digital 5v signal which feeds the c/s output buffer b1 and the other inte rnal circuit blocks, the vertical, back porch and odd/even functions. the vertical circuit senses the c/s edges and initiates an integrator which is reset by the shorter horizontal sync pulses but times out the longer vertical sync. pulse widths. the internal timing circ uits are referenced to i ot and v r3 , the time-out period being inversely proportional to the timing current. the vertical output pulse is started on the first serration pulse in the vertical interval and is then self-timed out. in the absence of a serration pulse, an internal timer will default the start of vertical. the back porch is triggered from the sync tip trailing edge and initiates a one-shot pulse. the period of this pulse is again a function of i ot and will therefore track the scan rate set by r set . the odd/even circuit (o/e) comprises of flip flops which track the relationship of the horizontal pulses to the leading edge of the vertical output, and will switch on every field at the start of vertical. pin 7 is high during the odd field. loss of video signal can be detected by monitoring the c/s output. the 50% level of the previous video signal will remain held on the s/h capacitors after the input video signal has gone and the input on pin 2 has defaulted to the clamp voltage. consequently, th e c/s output will remain low longer than the normal vertical pulse period. an external timing circuit could be used to detect this condition. block diagram figure 13. standard (ntsc input) h. sync detail *note: rset must be a 1% resistor. c sync out 1 a1 v r1 clamp 3-pole filter f1 2 video in c 1 i 1 i ot c1 + - c2 v r2 i ot cs s/h r1 r2 vtip vbp vertical detect i ot v r3 v r3 v r2 v r1 v ref v r4 i ot i tr i ref r3 rset rset back porch detect 3 4 5 6 7 8 i ot v r3 d2 b3 a2 - + b4 o/e detect odd/even out v dd v dd vertical out gnd q1 burst/back porch out b1 el4581
9 fn7172.2 november 12, 2010 el4581 small outline package family (so) gauge plane a2 a1 l l1 detail x 4 4 seating plane e h b c 0.010 b m ca 0.004 c 0.010 b m ca b d (n/2) 1 e1 e n n (n/2)+1 a pin #1 i.d. mark h x 45 a see detail ?x? c 0.010 mdp0027 small outline package family (so) symbol inches tolerance notes so-8 so-14 so16 (0.150?) so16 (0.300?) (sol-16) so20 (sol-20) so24 (sol-24) so28 (sol-28) a 0.068 0.068 0.068 0.104 0.104 0.104 0.104 max - a1 0.006 0.006 0.006 0.007 0.007 0.007 0.007 0.003 - a2 0.057 0.057 0.057 0.092 0.092 0.092 0.092 0.002 - b 0.017 0.017 0.017 0.017 0.017 0.017 0.017 0.003 - c 0.009 0.009 0.009 0.011 0.011 0.011 0.011 0.001 - d 0.193 0.341 0.390 0.406 0.504 0.606 0.704 0.004 1, 3 e 0.236 0.236 0.236 0.406 0.406 0.406 0.406 0.008 - e1 0.154 0.154 0.154 0.295 0.295 0.295 0.295 0.004 2, 3 e 0.050 0.050 0.050 0.050 0.050 0.050 0.050 basic - l 0.025 0.025 0.025 0.030 0.030 0.030 0.030 0.009 - l1 0.041 0.041 0.041 0.056 0.056 0.056 0.056 basic - h 0.013 0.013 0.013 0.020 0.020 0.020 0.020 reference - n 8 14 16 16 20 24 28 reference - rev. m 2/07 notes: 1. plastic or metal protrusions of 0.006? maximum per side are not included. 2. plastic interlead protrusions of 0.010? maximum per side are not included. 3. dimensions ?d? and ?e1? are measured at datum plane ?h?. 4. dimensioning and tolerancing per asme y14.5m - 1994
10 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn7172.2 november 12, 2010 el4581 plastic dual-in-line packages (pdip) mdp0031 plastic dual-in-line package symbol inches tolerance notes pdip8 pdip14 pdip16 pdip18 pdip20 a 0.210 0.210 0.210 0.210 0.210 max a1 0.015 0.015 0.015 0.015 0.015 min a2 0.130 0.130 0.130 0.130 0.130 0.005 b 0.018 0.018 0.018 0.018 0.018 0.002 b2 0.060 0.060 0.060 0.060 0.060 +0.010/-0.015 c 0.010 0.010 0.010 0.010 0.010 +0.004/-0.002 d 0.375 0.750 0.750 0.890 1.020 0.010 1 e 0.310 0.310 0.310 0.310 0.310 +0.015/-0.010 e1 0.250 0.250 0.250 0.250 0.250 0.005 2 e 0.100 0.100 0.100 0.100 0.100 basic ea 0.300 0.300 0.300 0.300 0.300 basic eb 0.345 0.345 0.345 0.345 0.345 0.025 l 0.125 0.125 0.125 0.125 0.125 0.010 n 8 14 16 18 20 reference rev. c 2/07 notes: 1. plastic or metal protrusions of 0.010? maximum per side are not included. 2. plastic interlead protrusions of 0.010? maximum per side are not included. 3. dimensions e and ea are measured with the leads constrained perpendicular to the seating plane. 4. dimension eb is measured wi th the lead tips unconstrained. 5. 8 and 16 lead packages have half end-leads as shown. d l a e b a1 note 5 a2 seating plane l n pin #1 index e1 12 n/2 b2 e eb ea c
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